(1) Field of the Invention
This invention relates to a method of fabricating integrated circuits and other electronic devices on semiconductor substrates. More particularly, the invention relates to an improved process for forming contact holes on semiconductor substrates.
(2) Description of Related Art
In the fabrication of semiconductor integrated circuits multilevel integration structures are used to connect the various devices in the circuits. As circuit density increases very large scale integration (VLSI) and ultra-large scale integration (ULSI) are used to interconnect the devices in integrated circuits fabricated on semiconductor substrates and the feature sizes of device components have decreased to 0.1 micron and less. This is particularly true for the contact holes required to connect devices between levels in multilevel structures. Therefore, fabrication processes for achieving VLSI and ULSI levels of integration must be capable of reliably forming contact holes between successive levels, where the contact holes have dimensions of the order of 0.1 micron or less in diameter.
An important challenge in the fabrication of multilevel integrated circuits on semiconductor substrates is to develop masking and etching technologies which allow reliable formation of semiconductor devices, interconnection conducting patterns, and interlevel contact holes which have dimensions of 0.1 micron on less. The masking technologies and the etching technologies must be compatible and result in high fabrication process yield and minimum process cost. In order to minimize cost, fabrication tool throughput must be maximized. Therefore, sequential processing in the same fabrication tool, without necessity to transfer to additional tools, is desirable and leads to reduced product cost.
As device feature size is reduced to 0.1 micron and less, the ability to achieve good image resolution in high density, small pitch patterns requires that the photo resist exposure and imaging processes be performed on a thin photo resist imaging layer. However, when etching features in thick layers, such as ILD (Inter-Level Dielectric) layers, thin photo resist masks are inadequate and schemes to provide more robust masking layers are required.
When circuit density requires that contact holes be of the order of 0.1 micron or less in diameter, resist masking schemes which use a single organic ARC (anti-reflection coating) layer or a single inorganic ARC layer are not adequate. Such single layer ARC schemes result in irregularly shaped etched holes having severe striations which can then contribute to shorting between adjacent contact holes.
Also, when using a bi-level resist structure, comprising a top imaging layer and a bottom dry developed organic layer, as the mask for plasma etching holes in silicon oxide using conventional gaseous mixtures of CxFy, argon, and O2 the top imaging layer is not removed by the silicon oxide etch process and a residue forms on the top of the top imaging layer during the etching of the silicon oxide. This residue further impacts the successful removal of the top imaging layer by subsequent O2 ashing processes and degrades the fabrication process yield.
The present invention is directed to an improved method of etching very small contact holes through dielectric layers used to separate patterned conducting layers in multilevel integrated circuits formed on semiconductor substrates. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which can be used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. Contact holes formed using this improved method may be used to make contact to active devices formed within the semiconductor substrate or the contact holes may be used to make contact between successive layers in multilevel integrated circuit structures.